DATE 2007 Workshop - Call for Participation

CALL FOR PARTICIPATION

Overview -- Workshop Description -- Program Elements -- Participation & Registration-- Information -- Workshop Program -- Poster Sessions -- Important Notice

Overview

The Design, Automation, and Test in Europe conference and exhibition is the main European event bringing together designers and design automation users, researchers and vendors, as well as specialists in hardware and software design, test and manufacturing of electronic circuits and systems. The conference includes plenary invited papers, regular papers, panels, hot-topic sessions, tutorials and workshops, two special focus days and a track for executives. Friday Workshops are focusing on emerging research and application topics. At DATE 2007, one of the Friday Workshops is devoted to Diagnostic Services in Network-on-Chips. This one-day event consists of a plenary keynote, regular and poster presentations, and a panel session.

Workshop Description

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Network-on-Chips (NoCs) are emerging as a new on-chip communication paradigm. Diagnostic services, such as test, debug, and on-line monitoring, are becoming an important factor in designing next-generation NoC-based systems. The NoC infrastructure itself requires diagnostic services, and can also be used to support those for the entire system. Although significant research has been done in NoC design, there are many open and pressing issues regarding diagnostic services. The focus of this workshop is to explore them and their implications on system design.

Program Elements

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The workshop program contains the following elements.

A keynote address: 'New Trends in Networks on Chips' by Giovanni De Micheli, EPF Lausanne, CH
Two invited talks

'Infrastructure IP for Network on Chip' by Yervant Zorian, Virage Logic, US
'Impact of Diagnostic Services on NOC Architectures and Design Flows'
by Kees Goossens, NXP Semiconductors, NL

Two sessions with in total five regular presentations
Two poster sessions (submission still open till March 15, 2007 or until poster slots are filled; in-topic submissions are selected on 'first-come-first-serve' basis; submission by e-mail to Program Chairs)
A panel session discussing the share of infrastructure in future SoCs

Participation & Registration

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You are invited to participate in the workshop. Participation requires registration and a registration fee. Discounted registration will be available through the DATE'07 web site only from December 2006 until about one month before the event. Full-fee registration will also be possible on-site in Nice, France. Check the DATE web site (http://www.date-conference.com/registration/) for rates and other information. Registration includes luncheon, coffee breaks, and an electronic version of the Workshop's Digest of Contributions, containing extended abstracts, papers, slides, posters.

Information

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Erik Jan Marinissen
General Chair
NXP Semiconductors
Corporate Research
High Tech Campus 5 (M/S WAY-41)
5656AE Eindhoven, The Netherlands
E-mail: erik.jan.marinissen@philips.com

Axel Jantsch
Program Co-Chair
Royal Institute of Technology
Department of ECS
School for Information and Communication Technology
Electrum 229, SE-164 40 Kista, Sweden
E-mail: axel@kth.se

Nicola Nicolici
Program Co-Chair
McMaster University
Department of ECE
1280 Main Street West - ITB/A210
Hamilton, ON L8S 4K1, Canada
E-mail: nicola@ece.mcmaster.ca

Workshop Program

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FRIDAY APRIL 20, 2007
8:30 am - 9:30 pm	Session 1: Opening Session Welcome Address Keynote Address: New Trends in Networks on Chips G. De Micheli - EPF Lausanne, CH The field of Networks on Chips has received a tremendous interest in the recent years, due to the downscaling of semiconductor technology. Indeed, while NoCs are desirable in a 90nm technology, they become a necessary component for 45nm SoCs, because structured interconnect is needed to deliver performance and error resiliency. This talk will cover the recent trends in circuit and network technologies with specific emphasis on error resilience and error control. We will address the main techniques for making NoCs reliable and fast and show trends in this area.
9:30 am - 10:30 pm	Session 2: Invited Talks 9:30 am: Infrastructure IP for Network on Chip Yervant Zorian - Virage Logic, US Today's NOCs necessitate embedding dedicated IP blocks, called Infrastructure IP or diagostic services into the NOC design. These IP blocks are meant to ensure the manufacturability of a NOC to achieve adequate levels of yield and reliability. The Infrastructure IP leverages the manufacturing knowledge and feeds back the information into the design or manufacturing phases. This presentation analyzes the key trends and challenges resulting in manufacturing susceptibility and field reliability that necessitate the use of such Infrastructure IP. Then, it concentrates on few examples of such embedded IPs for detection, analysis and correction. 10:00 am: Impact of Diagn. Serv. on NOC Architectures and Design Flows Kees Goossens - NXP Semiconductors, NL The communication-centric design paradigm states that networks on chip (NOC) are the focal point of SOC design. NOCs provide all communication between the IPs. IPs are decoupled from each other, and from the interconnect through the use of transaction-based design and managed performance (hard or soft guaranteed throughput and latency). Besides moving user data around, NOCs are ideally placed to provide other services that are global, i.e. span the SOC. Examples, are monitoring for diagnosis, debug, performance or QoS regulation based on transactions or otherwise. Besides user information also other data can make use of the NOC, such as for control and configuration, power management, test vectors transport. The use of a NOC for these additional services imposes new requirements and constraints on the NOC architecture and design flow. In this talk we give a number of examples of new services, and the impact they may have.
10:30 am - 11:00 am	Poster Session 1 (Coffee & Tea Break)
11:00 am - 12:30 pm	Session 3: On-Line Monitoring 11:00 am: Cost-Effective Network-on-Chip Design Using Traffic Monitoring System K. Kim, D. Kim, K. Lee, H.-J. Yoo - Korea Advanced Institute of Science and Technology (KAIST), KR 11:30 am: A Time-Triggered System-on-a-Chip Architecture with Integrated Support for Diagnosis C. El-Salloum, R. Obermaisser, B. Huber - Vienna Univ. of Technology, AU 12:00 pm: Dynamic Software-Assisted Monitoring of On-Chip Interconnects G. Kornaros, Y. Papaefstathiou, D. Pnevmatikatos - Technical Univ. of Crete, GR
12:30 pm - 1:30 pm	Lunch
1:30 pm - 2:30 pm	Session 4: Test and Reliability 1:30 pm: Improving NoC-Based Testing Through Compression Schemes E. Cota - UFRGS, BR; J. Dalmasso, M.-L. Flottes, B. Rouzeyre - LIRMM, FR 2:00 pm: Benchmarks for NoC Test and Reliability C. Grecu, A. Ivanov - Univ. of British Columbia, CAN; A. Jantsch - KTH Stockholm, SE; P. Pande - Washington State Univ., US
2:30 pm - 3:00 pm	Poster Session 2 (Coffee & Tea Break)
3:00 pm - 4:00 pm	Pannel Session: 10 or 90? The Share of the Infrastructure in Future SoCs Moderator: G. Martin - Tensilica, US Panelists: L. Benini - Univ. Bologna, IT A. Crouch - Inovys, US R. Marculescu - Carnegie-Mellon Univ., US B. Vermeulen - NXP Semiconductors, NL
4:00 pm	Close

Poster Sessions

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Poster Sessions 1 and 2

Networking-Based Testing and Diagnosis of Complex System on Chips
O. Laouamri, C. Aktouf - DeFacTo Technologies, FR

DfT for the Reuse of NoCs as a Test Access Mechanism: an Alternative Method for Low Cost Networks
A.M. Amory, M.S. Lubaszewski - UFRGS, BR; F. Ferlini, F.G. Moraes - PUCRS, BR

A Reconfigurable Diagnostic Infrastructure for NoCs
L.-B. Chen, C.-F. Kao, Y.-T. Lin, C.-H. Lin, C.-C. Wang, W.-C. Shiue, I.-J. Huang - Natnl. Sun Yat-Sen Univ., TW

STARS: A System for Tuning and Actively Reconfiguring SoC Links
G. Diamos, S. Yalamanachili - Georgia Institute of Technology, US; J. Duato - Univ. Politecnica de Valencia, ES

Using Emulation for System Model Analysis
P. Ellervee, A. Arhipov, U. Reinsalu - Tallinn Univ. of Technology, EE

Avoiding Router Crash Faults in NoCs at Design Level
A.P. Frantz, M. Cassel, F.L. Kastensmidt, L. Carro, E. Cota - UFRGS, BR

On-Line Test Methodology for MP-SoC Platforms
P.P. Pande - Washington State Univ., US; C. Grecu, A. Ivanov - Univ. of British Columbia, CAN

Deterministic Traffic Generator for Network-on-Chip Simulator
M. Tagel, G. Jervan - Tallinn Univ. of Technology, EE

A Multi-Resolution Bus Trace Analyzer for Microprocessor-Based SoC Development
C.-F. Kao, C.-H. Lin, I.-J. Huang - Natnl. Sun Yat-Sen Univ., TW

A Cache-Based Approach for Program Address Trace Compression
C.-F. Kao, I.-J. Huang - Natnl. Sun Yat-Sen Univ., TW

On-Line Health Monitoring via Statistical Clustering of On-Chip Communication
J.D. Lee, P.S. Bhojwani, R.N. Mahapatra - Texas A&M Univ., US

On-Line Reconfigurable Self-Timed Links for Fault-Tolerant NoC
T. Lehtonen - Turku Centre for Computer Science, FIN; P. Liljeberg - Univ. of Turku, FIN; J. Plosila - Academy of Finland, FIN

On Test Port Selection for NoC-Based Systems
C. Liu - Univ. of Nebraska-Lincoln, US; Q. Xu - Chinese Univ. of Hong Kong, HK

Analyzing Failure Modes (and Related Effects) in Network-on-Chip
R. Mariani - Yogitech, IT

Test Wrapper Design that Allows a Core to be Tested via a Network-on-Chip or Other Functional Interconnect,
P. Ren, G. Gaydadjiev - Delft Univ. of Technology, NL; A.M. Amory, M. Lubaszewski - UFRGS, BR; E.J. Marinissen, K. Goossens, S.K. Goel - NXP Semiconductors, NL; F. Moraes - PUCRS, BR

Graphical Environment to Network-on-Chip Communication Debug
A.P. Trujillo, Autonomous Univ. of Barcelona, ES

Application of De Bruijn Graphs to NOC Design
D. Pradhan - Univ. of Bristol, UK

An External Diagnosis Method for Network-on-a-Chip
J. Raik, V. Govind, R. Ubar - Tallinn Univ. of Technology, EE

Behavioral Abstractions of Signal Transition Protocols for On-Line Testing
D. Sokolov, D. Koppad, A. Bystrov, A. Yakovlev - Univ. of Newcastle, UK

Advanced Compact Modular Systems Based on New Diversified and Convergence Technologies
V.I. Vinogradov - INR RAS, RUS

A Debug Probe for Concurrently Debugging Embedded Cores and Inter-Core Transactions in NoC-Based Systems
Q. Xu - Chinese Univ. of Hong Kong, HK

A Novel Self-Routing Reconfigurable and Fault-Tolerant Cell Array
X. She, M. Zwolinski - Univ. of Southampton, UK

Important Notice

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The workshop has secured 30 poster locations. In the current program, only 22 poster slots are filled. Poster submission will stay open till March 15, 2007 or until all poster slots are filled. Submission is done by sending a (maximum) two-page abstract by e-mail to the Program Chairs. Acceptance is based on an in-topic review, followed by 'first-come-first-serve' selection.

Short or preliminary submissions can be replaced by extended abstracts or even full papers for inclusion in the electronic Digest of Contributions until March 31, 2007. Submission implies willingness to register for and attend the workshop in order to present a poster.

For more information, visit us on the web at: http://www.date-conference.com/

The Design, Automation and Test in Europe Conference and Exhibition (DATE 2007) is sponsored by the European Design and Automation Association, the EDA Consortium, the IEEE Computer Society (TTTC), (CEDA), ECSI, RAS and ACM SIGDA.